Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 12,760 értékelés alapján az ügyfelek 4.76 / 5 csillagot adtak Verilog / VHDL Designers szabadúszónknak.
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    Devlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor

    €282 (Avg Bid)
    €282 licitátlag
    9 árajánlat
    QPSK based digital communication 1 nap left
    HITELESÍTETT

    QPSK modulation and demodulation with Turbo Encoder/Decoder, Interlever, Channel Estimator, Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design development) on Zynq 7035 and 7030. Linux Based OS to make Linux OS executable files. Hardware: Zynq 7030 and 7035 FPGA and AD9361 Transceiver.

    €6438 (Avg Bid)
    €6438 licitátlag
    7 árajánlat
    Connecting sensor with lattice FPGA 1 nap left
    HITELESÍTETT

    To interface lattice FPGA with ultrasonic sensor (5 )and lidar sensor(4) with the provision for connecting an MIPI based camera module (no AI stuffs),the FPGA would be connected to stm32h7 via SPI interface . More details via chat including the sensor type

    €137 (Avg Bid)
    €137 licitátlag
    5 árajánlat

    Set up the frequency of the HCLK clock to 96MHz and the frequency of the PCLK1 peripheral clock to 24MHz, respectively, using the HSI (16MHz) clock source. Program the microcontroller such that you will be able verify the HSI clock and the PLL clock, respectively, on pin MCO1 (PA8). Part ii Set up the frequency of the HCLK clock to 120MHz and the frequency of the PCLK1 peripheral clock to 30MHz, respectively, using the HSE (8MHz) clock source. Program the microcontroller such that you will be able verify the HSE clock and the PLL clock on pin MCO2 (PC9). Task Two Port D (PD7…PD0) is designated as output port for this task. 1. Draw a detailed schematic diagram for Task Two. It should include IC part numbers, IC pin numbers and Header P1 pin labels, respectively. All signal lines shou...

    €459 (Avg Bid)
    €459 licitátlag
    17 árajánlat

    Set up the frequency of the HCLK clock to 96MHz and the frequency of the PCLK1 peripheral clock to 24MHz, respectively, using the HSI (16MHz) clock source. Program the microcontroller such that you will be able verify the HSI clock and the PLL clock, respectively, on pin MCO1 (PA8). Part ii Set up the frequency of the HCLK clock to 120MHz and the frequency of the PCLK1 peripheral clock to 30MHz, respectively, using the HSE (8MHz) clock source. Program the microcontroller such that you will be able verify the HSE clock and the PLL clock on pin MCO2 (PC9). Task Two Port D (PD7…PD0) is designated as output port for this task. 1. Draw a detailed schematic diagram for Task Two. It should include IC part numbers, IC pin numbers and Header P1 pin labels, respectively. All signal lines shou...

    €11 / hr (Avg Bid)
    €11 / hr licitátlag
    4 árajánlat

    For 10 years, poor FPGA BTC mining implementations, completely missed the big picture with excessively large, slow, power hungry designs. Researchers presented dozens of papers on how to make this better, completely missing the mark. This is your chance to get it right. Read this paper , then and look at their Verilog here to get a good understanding about state of the art FPGA BTC mining with verilog. Then apply that to YOUR FORK of the old standard in with an updated proxy for getwork. Clues follow to make FPGA BTC mining faster, smaller, and lower power, so that you will have REAL bragging rights for the fastest, smallest, lowest power FGPA miners. Goal >10x speed up. 1) The SHA256 compression is seeded with 256 bits of very random constants and forms a large shift register as t...

    €575 (Avg Bid)
    Kiemelt Garantált Rejtett Top verseny
    €575
    11 pályamű

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