Hi,
I am good in VHDL/Verilog programming. I did couple of projects of designing fir filter using matlab and vhdl. I have also experience of using block RAM and floating point ip core in this kind of project.
Please elaborate the exact input and output of the FPGA, sampling frequency and ADC quantization levels to proceed further.
Will I have to set the filter coefficient or you will share the same? In case the first one, please share the filter specification like cuttoff frequency, passband and stopband ripple etc.
Thanks,
Mastor