Voice scrambler/descrambler

I'm electronics and electrical communications engineering TA with 12+ years of experience. experienced in implementing complete communication transmitter/receiver chains including voice coding/decoding - interleaver - scrambler - channel coding/decoding even the security algorithms implementation over the FPGA. experienced with the Spartan 3- Spartan 6A-ZYNQ - Vertex 5 (Xilinix Side) - Cyclone 3 (Altera Side) would help you writing the ucf - sdc for the hardware constraints tell me the exact details and I'll help you writing the VHDL/Verilog of the project + Simulation on the Vivado/Altera Max Plus/ISE + Synthesis and document the work perfectly

Hi, I am a FPGA design engineer by profession. I have worked on the Scrambler and Descrambler architecture for my various communication projects. My Proposed schedule is as follows: Understanding the architecture/ Specification / Requirement (2 Days) Proposed architecture/ Review from your side (2 Days) Updated Design/ RTL Implementation (4 Days) Simulation/ verification (2 days)(1 st payout) Design document (3 days) (2nd payout) (Tentative schedule may be reduced based on the quick results) Please feel free to contact for the further discussion Regards Hari

design a scram a discram for a analogic input and analogic output with simple components avalibles easy