> Have a experienced layout team who can work for this project with high quality and deliver the same before deadline by meeting designer expectation.
> To see our expertise and quality, am ready to work on a small demo layout block for your design with your EDA tools and setup.
> 6 years of experience in the areas of Analog layout designing, Physical designing, physical verification domain and also worked on 350 nm to till 7nm ff project.
> Familiar with Cadence Virtuoso (L, XL), Virtuoso space based router (VSR), Constrain driven layout, Place and route in Encounter and assura, PVS, caliber for physical verification.
> Worked on the layout of data converters (ADC, DAC), power management blocks (BGR, LDO etc.), EFUSE, Dual EFUSE, switching regulators, Serdes (DSI), pacemaker and failure analysis test chips.
> Experienced with doing layout design from PAD & ESD cells placements, area estimation of top & block level, layout designing, verifications as well as providing support to foundry during release.
> Experienced with handling tape out activity and communicating with different foundries GF, Magnachip, Samsung and TSMC till GDS goes for mask making.