Based on my documents, I want you to have my past university student electronic circuit design and simulation project reproduced in Cadence Virtuoso.
It is a minimalist project, about 5 parts.
You should have knowledge of Cadence Virtuoso 6 software.
The electrical circuit in Cadence Virtuoso is using 350 nm (0.35um) Technology design kit.
The schematics, simulations, and layout will be provided once the job is finished.
Required to have strong experience in block-level designs, top level integration and Floorplanning , along with deep understanding of layout techniques.
Design rules, ESD, isolation, device matching and low parasitic.
A solid track record in full chip assembly and verification and cadence skill programming is a plus.
Producing and delivering high quality layouts .
Floorplanning, block level layout, top level integration and pad ring layout of RF/high speed blocks.
Coordinating layouts block resources and support other team members.
Conducting tape-out verification tasks which include: DRC, ANT, DUM and LVS.
Preparing technical reviews and product documentation.
Working with cross functional teams to deliver IC Products.
Hello sir,
I am an IC Mask layout Design Engineer. I have experience to work in TSMC 7/16/22/130/180 nm node. Also worked with NCSU PDK, ASAP7 PDK
Cadence Virtuoso I have worked so far IC CAD 12.2,12.3 also Version of 5.1, 6.1.4,6.1.6
I have licensed cadence Virtuoso 6.1.4
I do have extensive knowledge in block to top level layout design, LVS, DRC solving. Please see my portfolios
Waiting for your response
Thanks in advance...
€166 EUR 3 napon belül
5,0 (1 értékelés)
2,0
2,0
7 szabadúszó adott átlagosan €162 EUR összegű árajánlatot erre a munkára
Hi, I am a professional electrical engineer I know all about circuit and layout design on cadence mentor and synopsys and have all the required cad tools on my laptop I can finish your task quickly and efficiently, you can see my works in circuit design in my portfolio.
Thanks
I have graduated from the best university of India with masters in VLSI Design. I hold multiple patents. Right now, I work as an Analog Design Engineer at Texas Instruments. I have good knowledge in Cadence and I have worked on Bandgap. ADCs, DACs, Oscillators etc..
Hope I will be able to help you
I have gone through full custom design of 4-bit Linear feedback Shift Register ( LFSR ) in Cadence Virtuoso using AMI 0.6 Micrometer technology.
I have been experienced in schematic design entry, layout, design rule checking, layout vs schematic and post layout simulation of each individual cell throughout the design.
For the tools, I used Diva for DRC and LVS, and SpectreS for simulation
The total design was 156 transistor, 5 cells, 3 layers of metal and running at 1 GHz. I'd be happy to send you the project report if you wish.
I could also verify the functionality of the design on Xilinix ISE or Altera Quartus using verilog and simulate it on Isim before jumping at Cadence.