1. To generate pseudo random numbers, Iam planning to use a LFSR. I have other ways in mind though. I assume that the pass through block for axi verification IP is inside the core Threshold_0.
Relevant Skills and Experience
System Verilog, Xilinx Vivado, Low power vlsi Architectures, FPGA Flow. I have a work experience of 2 years.
Proposed Milestones
€48 EUR - architecture design in a day, verilog implementation in 3 days, Verification 3 days synthesis 1 day.