Verilog vhdlmunkák

i have a matlab code that will do analysis of any colourful object like its colour ,parameters.i want to do some changes in this code and want to convert it into c++ or VHDL project involves implementing a image processing system on FPGA microprocessor ARM to determine how many multiplers time required to implement the can we do the parallel processing to increase the i want all this to be done on software OR any other image analysis code implemented on FPGA ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables

PAL/NTSC video is samples at 27 MHz @ 10 bits and stored in a circular buffer, buffer does have a length of two video lines (128us). The video is simply processed and send out to a DAC back into normal PAL/NTSC. FPGA used is XC3S50AN. Your required to write the VHDL Code for the FPGA used. Video Codec used is ADV7202 from Analog devices. Control processor from Microchip is communicating with the FPGA for sending commands (type of processing needed). More details will be given to the winner of the Bid.

...board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc **(see enclosed updated document). **This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This was a 4 phase project and hereby the first to show: Phase-1 project. Former bidders requsted to place a bid per all four phases. This bid calls for Phase-1 only and after completion by winner/s we will issue the next phase bid and so on. The attached document describes all fours phases. Pls. your attention to bid on phase-1 only. ...

...100K) tested board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc (see enclosed document). This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This is a 4 phase project. Coder requsted to place a bid per each phase. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web site...

Digital Engineer, FPGA/VHDL/C++, can result in shared ownership of the project. An ongoing hardware development project needs personnel for debugging/completing a design based on FPGA. Job Description Work as a VHDL developer on a hardware development team to complete a leading edge development project building next generation network security systems. Candidates shall meet following qualifications: Good general programming skills Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Good understanding of computer architecture About Us Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most ad...

**An ongoing hardware development project needs personnel for debugging/completing a design based on FPGA.** **Job Description** Work as a VHDL developer to completing a design based on FPGA. ## Deliverables Candidates shall meet following qualifications: **Xilinx FPGA devices and design toolsets. ****FPGA code design using the VHDL language. Strong architectural design skills. ** Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Code simulation and verification using a variety of development toolsets. **About Us** Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most advanced in ...

please check attachment for detail

I need the program for an alu model of blackfin processor ADSP BF533. So, that I can run and simulate it using XILINX. It must be synthasizable. You can just e-mail me the code. ## Del...under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Windows XP and VISTA are the supporting ones. ISE - XILINX of version 8.2i is the software you need. It contains VHDL model aswell. useful links are... When you download xilinx you'll find a tutorial file in the destination folder. It may help you.

Here is the specification: Must be finished by December3.

Witam serdecznie potrzebuje prosty program w jezyku VHDL wiecej informacji na email.

I have a small project that I need done by Verilog that can work on Quartus II software. it basically consists of the mastermind game, where a user inputs a sequence of 4 colours and the other user must guess the 4 sequence of colours by the first user. I have a VGA module already implemented. As I wanted to show this on the screen. so does anyone know how to do this??? I didn't know what to pick for this since Verilog is not listed.

Poszukuję osoby ze znajomością Vhdl-a. Proszę o kontakt w celu omówienia szczegółów.

I need some verilog projects that you have done in the past and a tutorial on how to program in verilog. You can put the projects that you have previously done in a word document and write about how you solved each problem. I would like to see at least 5 projects with increasing complexity. I'm trying to train some entry level engineers how to develop programs in verilog. If you are interested in this please send me a sample of your work so I can choose the best bidder. I don' t want someone to just copy some code off the internet and write about it. I want someone who knows verilog and can either develop some projects for me or has some projects done already that I can buy from them.

Please see the attached zip file ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ...

We require porting of a design which uses 3 Cyclone FPGAs into one Cyclone3 FPGA, source code for the firmware is available for the coder, knowledge of VHDL/Verilog along with hardware level cyclone3 knowledge required.

Design PCI devices, with following specifications: 1. Design PCI arbitration logic for initiator 1 and initiator 2 on PCI Bus 2. Design the initiators and targets that can perform following cycles 3. Design all the signals required 4. Initiator1 and target1 are same devices 5. Initiator2 and target2 are same devices 6. Initiator 1 is higher priority and gets the 1st grant. more details in attachment PCI-clocks is 33 MHZ Points to be evaluated 1. Simulation results 2. Test bench and code

I have some code that I need fixed. I cannot figure out the problem because my VHDL is not very good. Please correct in Xilinx. The code is for an piecewise implementation of ln(x) using integer arithmetic. I can provide the C file for it if needed. Need it done ASAP. ## Deliverables I have included the files below.

Witam mam do napisania prace z języków opisu sprzętu. Temat: Opracowanie systemu mikroprocesorowego. Posiadam materiały i troszke mam napisane mogę to udostępnic. Nie polega to na zaprojektowaniu system mikoroprocesorowego ale należy przeprowadzić symulacje.

Witam mam do napisania prace z języków opisu sprzętu. Temat: Opracowanie systemu mikroprocesorowego. Posiadam materiały i troszke mam napisane mogę to udostępnic. Zakres: przygotowanie modeli oraz wizualizacji wyników w VHPI, PLI.

Witam mam do napisania prace z języków opisu sprzętu. Temat: Opracowanie systemu mikroprocesorowego. Posiadam materiały i troszke mam napisane mogę to udostępnic. Zakres: przygotowanie modeli oraz wizualizacji wyników w VHPI, PLI.

Take an RGB image and split it into 8*8 blocks in Matlab for me. Send me screenshot of the output.? You can read the image in matlab using imread command....then it will store in a variable...then by using csvwrite command you can write data into a file. And if you know how to use this ...split it into 8*8 blocks in Matlab for me. Send me screenshot of the output.? You can read the image in matlab using imread command....then it will store in a variable...then by using csvwrite command you can write data into a file. And if you know how to use this data as input in a DCT block in VHDL for JPEG Compression, please tell me otherwise just do the first part.? Need it fast. ## Deliverables Must be in Matlab or VHDL. I prefer VHDL but Matlab is good too. I'll pay hig...

i designed a datapath and now i need to simulate it with VHDL,but i dont enough time to learn it..just simulate it... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software? installation package that will install the software in ready-to-run condition on th...

I need someone with experience in TOR3 boards () who can help me finish the open source PCI gerber and BOM. I also need help finding the VHDL to program the Xilinx chip.

Hi everyone, I have project, Division by repeated Multiplication, the project is implement the Division by repeated multiplication algorithm in VHDL (IN STRUCTURAL CODE, NOT JUST BEHAVIORAL CODE). since I was running out of time, if there's anyone out there has been mastering on this or ever did this kind of project please help me. I will be so very thankfull by this. really. looking forward to your helps... Thanks, Regards, Steve. PS. I need the final code including the testbench and the syntesis result on the general purpose fpga (in terms of area, delay and energy consumption)

Convert this verilog project to vhdl ## Deliverables Convert a verilog project to vhdl

• Design in VHDL • Convolution • Correlation • Filtering • Implementation on an FPGA board

I am currently doing a project of which Im building a central heating prototype. this is done using FPGA spartan 3 starter kit. and I need help with programming it in VHDL. I have done all the hardware and includued everything in the file, all I need is the VHDL codes, for LCD interfacing, and programming a digital thermostat I used in my daughterboard and many other features you will find described in the file attached with this. Please have a look at my propsal and let me know if you can do it. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. ## Platform FPGA spartan 3 starter Kit.

need verilog code for:Ascii to hex convertion

...generate/interface the following signals SE, SDI, SDIFS, SDOFS, SDO, MCLK, SCLK. This is a starndard SPORT interface (much like SPI) so few of you may even have this already implemented. So you must generate the clock (using clock divider, code can be provided on request) to supply the clock to the AD73360, write Verilog code to interface with the AD73360 so that it is able to receive data from the ADC. I want to able to write registers and get values in NIOS processor. Basically you will write Verilog (NOT VHDL) code to interface to the ADC and provide C functions/program that will run in the NIOS processor. Functions must be able to 1. Write all registers 2. Read all registers 3. Read values of all 6 channels and save them in 6 integers Sampling rate...

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Please read the attachment the code requested is in the last two pages...

Please read the attachment the code requested is in the last two pages...

Please read the attachment the code requested is in the last two pages...

INTRODUCTION:? ? The project involves the implementation of the architecture of super scalar pipelined DLX (Delux) processor for the execution of certain instructions. The different instructions the processor would execute are:? ALU instructions:? ADD, SUB, AND, OR, XOR, SRA. We have signed, unsigned, and immediate type for ALU type instructions. I need for some types like ADDI, S...AND, OR, XOR, SRA. We have signed, unsigned, and immediate type for ALU type instructions. I need for some types like ADDI, SUBU. Etc. ? Branch Instructions:? BNEZ, BEQZ.? Load and store Instruction:? LH, SB, etc? Jump type Instructions: J, JAL. We have only four types in jump. Any two of them would be fine.? ? more info attached... ## Deliverables use xilinx software with verilo...

Zlecę napisanie prostej gry w AHDL lub gry podany po zaakceptoeaniu przez mnie oferty Założenia: -płytka ma sie komunikować z komputerem za pomocą portu USB, dostarczam moduły obsługujace te transmisję -stan autioamtu głównego ma być wyświetlany na wyswietlaczu LCD, dołączam moduł obsługujący.. Oferty,wraz z ceną proszę składać na portalu, z zainteresowanymi skontaktuję się osobiście

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"Automation of state reduction process of sequential circuits " is an engineering project. We have to write the code in VHDL language of any model like structural , behavioral or data flow methods. in this project, firstly we have to write a code how we reduce the states assuming approx 20 states and then including don't care states as well. after this , we have to implement this reduction on implication chart. we have to write a code for the implication chart as well to find out the final answer. I'm attaching some zip file ..you can go through them..ok ...you can view the process from pages 15 to 23..ok. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliver...

This is a straightforward project for anyone familiar with using the Altera DE 2 development board and the Quartus software.? The project is to help code a system using the drah and drop NIOS processor, read a voltage input, display using the lcd screen and drive a stepper output.? ? Coders who are familiar with vhdl, quartus and the altera cyclone 2 will find this very straightforward.

I need to do Soundex Algorithm in VHDL language in Xilinx software. A simple name as the input for example my name 'NAUFAL' => then will be converted based on the soundex algorithm and table => and will give the output of 'N160'. I already make the research and I will provide all the details needed such as the description of soundex, flowchart, and etc. Hope to hear from you asap. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Del...

I have three questions related with VHDL. YOu have to write the complete State machine and then VHDL code for each problem in the tool called "XILINX". The questions are not difficult. Please read the attached file for the description of each question. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop s...

2 questions to solve using VHDL, code must work properly though implementation is not important. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified i...

MPEG-2 video encoder project. I have the block diagram as well as the specifications. Need Verilog HDL coding for the encoder. Major blocks include Discrete cosine transform, Quantization, Run length encoding and Motion estimation. The input to the encoder is taken in YUV format from a camera source. A completed project would be paid $300. Deadline for this project is dec 25th, 2007. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be insta...

Please see attached document for details VHDL Code and Testbed for System Required (Simulation Optional) Simple Arithmetic operations Needed ASAP (within 24Hours) Thanks in advance! ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software inst...

I'm in need of a detailed guide to VHDL syntax. You can use this as a guide but don't put in any examples, just syntax. I don't want you to copy this link exactly either, put it into your own words. Here's the link, and add what's missing to this link: <> ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite. 1) Complete and fully-functional working

hey I wanted the vhdl code for the following..... could you help me out with this..... --Design and synthesize a simple vending machine on the Spartan 3 or Spartan 3E board with the following features: --􀂾 The vending machine has four products. They cost 75, 80, 85, or 90, cents each. Use the slider switches (SW0 thro SW3) to select one of the products. --􀂾 Use two of the seven segment displays (or the LCD) to display the cost of the product entered --􀂾 Assume the vending machine only accepts $1 bills. Press BTN0 to pay for the product. --􀂾 Dispense the product by activating an appropriate solenoid (turn on an LED for 1 second to indicate the specific product is being dispensed) --􀂾 Using the other two seven segment displays show the change required

Hi all, We are looking for a Software engineer which will cooperate with my company's engineers and developers, in the development of a new product. In general, the product is an electronic device which acts as a voltmeter. The selected engineer will have to write the software part for the used hardware. The technical knowledge required is as follow: VHDL Language, Xilinx or Altera tools, Modelsim for simulation, Writing Test benches. The most important issues are the candidate's communication skills and loyalty. The company team includes employees from all over the world (India, USA, Israel, Macedonia..), and therefore professionalism, commitment and dedication are required. This is a very serious and multi modules project with tight deadlines. Workers of...

Delhi public school problem ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's enviro...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement...

Hi all I'm having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isola...

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I have a design that needs verilog code written to act as a JTAG TAP Master. It gets commands and data from another chip and needs to output JTAG commands. This all needs to fit into a 64 macrocell CPLD. This project will be worked on together as I will provide logic traces and you will program the verilog so the jtag signal closely matches the logic traces. I wish for someone to be in Northamerica so the time-zones are close enough for real-time communications. Please send me a PM if you are interested and I will post the logic traces for you to examine. This project is VERY SIMPLE (how complex can you get with 64 macrocells =D)