Fpgamunkák

Hi Jeff I am looking to port a few of our imaging modules to an Altera Cyclone 3 platform. Let me know a time that works and I'll give you a call. Thanks Arvind

Hello, I need a VHDL design which converts the complete DDR2 SDRAM Memory to a 32-Bit FIFO. The target Memory is Micron MT47H32M16HR -25 or -3 speed grade. Target FPGA is Xilinx Spartan 6 XC6SLX25T-2CSG324C. Design should work in Xilinx ISE Simulator. Attached is the TOP VHDL file to give an idea how it looks like. Regards, Ersin ÖZALP

I need to implement 802.11 b/g in simulink using Xilinx blocksets and then by using Xilinx system generator translate it into verilog and implement the design on FPGA kit (possibly Virtex 6). I need complete design in working condition. If someone can help me please reply!!

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Create VHDL code for FPGA-use that is equivilent to the functional elements described within the Actel coreSDLC V3.0 handbook. The Actel coreSDLC V3.0 handbook will serve as the programmer's guide / handbook.

I need Verilog code for capturing images from NTSC camera (input is video camera), buffering images in external RAM on Nexys2 labkit (FPGA Spartan 3E XC3S500E FG320), and using the VDEC1 ADV7183B video decoder chip to convert from NTSC to YCrCb, then displaying the images on VGA monitor. Basically, the input to the VDEC1 will be NTSC, the output of this chip will be YCrCb, Then, the YCrCb should be converted to RGB to be buffered and displayed on the vga monitor. Attached is pdf of a very close project, but I need the output to be VGA (640 by 480) not SVGA. And definitions of the modules in verilog are povided in the zip file.

2 axis solar tracking circuit design using FPGA cyclone III FPGA Starter Kit. Need PCB layout, circuit design and programming details.

Design a Tetris vidoe game modules that can work on SPARTEN 3E FPGA using verilog. the code should run on xilinx ISE 13.2 , the labkit and VGA module is given for us. this is the complete requirement : A block diagram of the module if it is based on FSM, I want the FSM design. I want to the game to be controlled via the keyboard The scores should be displayed on the monitor. the file that I send was the template for the pong game that I did it before, so you can use it for the tetris game DOWNLOAD THE FILE FROM :

i looking for a person who can help me with vhdl codes ... then upload the codes to Altera's FPGA cyclone iii ...

A worker is needed to write a set of VHDL modules for latches, counters and decoders. Please see the attachment for details.

Bachelors in Engineering from a reputed institute with good academic record Having 6+ years experience in ASIC design & verification Good Knowledge on Tools like VMM, UVM, OVM, VERA Preferable SOC Verification. ASIC design experience with RTL coding in Verilog/VHDL, FPGA experience, FPGA Board bring, FPGA synthesis

I need 100 high quality technical articles on Hardware design, FPGA, Verilog, ASIC, Synthesis, simulation..etc. Only US$10 milestone. rest milestone payment will be after each 25 articles.

I am currently seeking a vendor to produce the following item turn-key complete with PCB layout, prototype, device drivers, etc ... We seek to design a PCB board with the following components: 32x Xilinx Spartan 6 or equivalent FPGAs 32x Heatsinks and cooling fans for each FPGA Cypress EZ-USB FX2 or equivalent Microcontroller EEPROM for Firmware MAC-EEPROM for non-erasable MAC address High-Speed USB Interface On-board Power Supply On-board Temperature Sensors Fast FPGA configuration using CPLD: 24MB/s via USB or better Would be best to be able to interconnect multiple boards. Applications: Runs cryptographic hashing functions(2 rounds of SHA256) on block header. Optimized for the following computations: Bioinformic calculations Monte Carlo meth...

...presentations and demonstrations of Cadence OrCAD platform products. This will also address the recent trend and cost effectiveness in PCB Design, High Speed design and Cadence OrCAD solutions. FEATURED PRODUCTS OrCAD PCB solutions for PCB design, PSpice and Signal Integrity design. WHO SHOULD ATTEND? ? PCB Designers ? Hardware Design engineers ? Electronics System designers ? FPGA Engineers ? Scientist- Analog/Mixed, Scientist- RF, Scientist-Digital ? Scientist- EMI/EMC, Scientist- System Design ? Electronics / Communications / Instrumentation Engineers ? Managers - Engineering / PCB design ? Engineers from electronic product company ? Design service engineers ? Electronics manufacturing Engineers Date: Friday, November 23 , 2012 Time: 9.0...

With dedicated OSD IC becoming increasingly rare we require a simple minimum chip count OSD to replace the functionality of these IC. Preferably either Microchip or FPGA based the project should take a standard video signal 1Vpp and overlay txt on top of it. Text should be ideally 28 char x 12 rows Text should be white with a small black border on each letter to make it easier to see on a white background. Text to be input via serial, TTL 5V levels. Control codes to be agreed. Will require buffering within the processor for seamless changes when txt is added or removed. 12V operation

Hi All I need someone help me to work Demonstrated on a Spartan-6 FPGA,using the Xilinx ISE Design Suite (Embedded Edition) () and write a small application for this project. After finish, sent me all data and write tutorial for me. Regards, Nam Le

Hi All, I have a project about embedded symtem: FreeRTOS and FPGA Xilinx. I need someone working all for project. Please email for me : for detail. Regards, Le Nam

Require a VHDL design to be optimized for placement, currently the logic is at 8ns with 5.5 (67%) delay down to routing. Three slices are sitting at 2.2ns & 1.5ns & 1.4ns respectively rest are < 0.5ns

...Design Services We provide professional electronic design services that specialize in new product and prototype development -Far East Outsourcing We offer far east manufacturing solutions through our partner affiliations. These provide options that will allow you to reduce costs in both the developmental stage and final product manufacturing. -FPGA/CPLD Design We provide complete FPGA VHDL development and simulation using Altera and Xilinx development tools. -PCB Layout Complete PCB layout, design, and manufacturing services. We work closely with the manufacturers to provide quality manufacturable products in the first stages of development. This means quick time to market for our customers. AVT designers util...

First of all take a medical image then select its region of intrest(ROI) apply compression algorithm then after compression extract (ROI) and aply encryption algorithm on ROI and place it on that place and similarly apply decryption.

This project generates Pulse Width Modulation Waveforms for electronic circuits using Field Programmable Gate Array(FPGA). The coding language used is VHDL on XILINX platform and testing done on ModelSim. PWM waves are majorily used in many electronic gadgets as a supply of clocking signals, mobile phones etc. Implementing it on a FPGA provides speed, high efficiency than other comparable technologies. Most important feature of this project is that this device can be used to provide CLOCK signal to 'N' number of other devices. Hence this device can function as a clock generator as well as Master-Slave clock generator to electronic circuits. A real life scenario where this PWM finds application is in TV, where the user tunes SLEEP option and the TV gets ...

This project generates Pulse Width Modulation Waveforms for electronic circuits using Field Programmable Gate Array(FPGA). The coding language used is VHDL on XILINX platform and testing done on ModelSim. PWM waves are majorily used in many electronic gadgets as a supply of clocking signals, mobile phones etc. Implementing it on a FPGA provides speed, high efficiency than other comparable technologies. Most important feature of this project is that this device can be used to provide CLOCK signal to 'N' number of other devices. Hence this device can function as a clock generator as well as Master-Slave clock generator to electronic circuits. A real life scenario where this PWM finds application is in TV, where the user tunes SLEEP option and the TV gets ...

anyone could help me finishing this project by the end of october 2012 .

i doing a image processing project on FPGA board . it would be very nice to have your expertise .. contact me hpalawow@

i m doing a image processing based on fpga project. it would be nice to have a expert to help me .. thanks please reply me hpalawow@

first of all we want interface ps2 keyboard in sparton 3E FPGA kit..then take image and encrypt it and show on vga lcd on the kit internal..

...The modules are interconnected but yet independent. ) • Program Architecture: Refer Job Description - II Position Title: Senior Embedded Hardware Architect Job Type: Contract (Full time: 4 months) Monthly Compensation: 40-70K INR Essential functions and responsibilities: • Applying knowledge in Analog & Digital design circuits. • Working on FPGA, PGA and microprocessor based board level designs. • Producing architecture that has sound hardware design with extended functionality. • Producing embedded hardware and refinements by identifying design objectives and issues; researching and developing embedded systems engineering techniques and approaches and verifying designs. • Architects optimized hardware for efficiency, integratio...

...The modules are interconnected but yet independent. ) • Program Architecture: Refer Job Description - II Position Title: Senior Embedded Hardware Architect Job Type: Contract (Full time: 4 months) Monthly Compensation: 40-70K INR Essential functions and responsibilities: • Applying knowledge in Analog & Digital design circuits. • Working on FPGA, PGA and microprocessor based board level designs. • Producing architecture that has sound hardware design with extended functionality. • Producing embedded hardware and refinements by identifying design objectives and issues; researching and developing embedded systems engineering techniques and approaches and verifying designs. • Architects optimized hardware for efficiency, integratio...

The NeTV is a piece of Open Source hardware which takes a HDMI signal in and allows custom images and text to be overlaid on the image before output. More information about the device can be found in the detailed information section. This project is to add support for common DVI resolutions to the Verilog code found at <> The resolutions that need to be added are; * 1024x768 @ 60Hz, 75Hz and 85Hz * 1280x720 @ 60Hz, 75Hz and 85Hz * 1280x800 @ 60Hz, 75Hz and 85Hz * 1366x768 @ 60Hz, 75Hz and 85Hz **The code will be tested by downloading the new firmware into a stock NeTV and trying to use the overlay feature on a DVI signal via passive DVI->HDMI and HDMI->DVI changers.** ## Deliverables To complete this project you may need to purchase a NeTV

The project will build a satellite modem from scratch ,The modem details can found at

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i have one mother board it is having ALTERA cyclone III family FPGA. I done most of the components layout, pin details. I need to draw the schematic (circuit) diagram for the same that is complete and sync all the components on that board. [Contact details removed by Admin]

The NeTV is a piece of Open Source hardware which takes a HDMI signal in and allows custom images and text to be overlaid on the image before output. More information about the device can be found in the detailed information section. This project is to add support for common DVI resolutions to the Verilog code found at <> The resolutions that need to be added are; * 1024x768 @ 60Hz, 75Hz and 85Hz * 1280x720 @ 60Hz, 75Hz and 85Hz * 1280x800 @ 60Hz, 75Hz and 85Hz * 1366x768 @ 60Hz, 75Hz and 85Hz **The code will be tested by downloading the new firmware into a stock NeTV and trying to use the overlay feature on a DVI signal via passive DVI->HDMI and HDMI->DVI changers.** ## Deliverables To complete this project you may need to purchase a NeTV

I want to get PCB layout of board like this: My schematic will have some minor changes, I'll send it nearest time. Could you write me approximate price and runtime of work. Could you help me to make first prototype of device?

my project is all about securing the house. this system not only detentes and notify the user about strainers but also controls the room the end the device will have a size of 10cmx10cm. this device is designed for this time based on micro controller but for the feature i am planning to change it with FPGA because it have better speed and want to add more functionality like door controlling system(i.e to have some thing like card or TAG to open the door ) and video Surveillance . Bay the way in this project tele surveillance is included,that means it will call to the intended person when an authorized person get into his hos when he is not around. most of the project part is done including the sensor part and micro controller part and tested .the difficult thing is that most

Looking for someone to build the architecture and firmware of a controller of an LED Matrix of 196x64 LEDs. This should include pwm emulation, fpga interfacing, speed optimization and color optimization. It should also include the development of a small driver to display png,jpeg,bmp images, fonts, geometries (circle, point, rectangles) NDA will be required.

The overall project is to generate an audio single sine wave or multiple sine wave to drive an inductive load with power range from 200 watts to 500watts, and frequency range from 300hz to 35khz. This particular project will dri...range from 200 watts to 500watts, and frequency range from 300hz to 35khz. This particular project will drive the amplifier FET's in H-Bridge configuratiion. The output of the FET will generate high power SINE wave, single frequency or dual mix frequency.(Frequency range 120Hz to 35Khz) Operating frequency are selectable using CPLD or FPGA, the output of CPLD or FPGA is PWM that will drive the FET driver. Several commands can be issued to the CPLD or FPGA like turn off the output and so on. Programmer will select proper dev...

You must have strong FPGA knowledge prior to bidding. I would like to develop an FPGA board to drive 4K x 2K LCD displays. The device will have 1 x DisplayPort 1.2 input (4 lanes at 5.4Gbps max 4096 x 2400) LVDS output (upto 8-channels at 10-bit) Please see attached PDF. You job is to write a feasibilty study for creating such a board. You will have to investigate available hardware, IP cores and consider the FPGA footprint and I/O requirements.

...information about the device can be found in the detailed information section. This project is to take the FPGA side of the system and change it into a USB based capture solution for HDMI and DVI. This task will require changes to both the Verilog code running on the FPGA and physical modifications to the board. The result of this project will be released under the same licenses to the NeTV device it's based on. * CC3.0-BY-SA license for PCB, mechanical design and schematics * BSD license for all Verilog code **This is an FOSS project, reusing compatibly sourced code is compatible is not only allowed, but recommend!** ## Deliverables # Conversion of NeTV device (Xilinx FPGA device) into a USB HDMI capture solution To complete this project yo...

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I'm working on a DisplayPort emulator that intercepts the AUX channel between a video adapter and a monitor. I need an expert on the DisplayPort specification and FPGA to give advice on the matter. ## Deliverables requirements notice: As originally posted, this project does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite.

HI, We have our own FPGA BOARD. We want come up in the market. we are providing in reasonable price. We covered Andhra pradesh in south zone rest of the city's. You can make 5000+ Rs in each sale; We required people with a zeal on Embedded systems or Fpga .

It is necessary to implement Quad-Artix7 XC7A200T FPGA Board with USB 3.0 Microcontroller optimized for cryptographic computations, it will be some-thing like the following FPGA Board: but instead of Spartan6 will be used Artix7 (XC7A200T-3FBG676CES9899) and will be added USB 3.0 Microcontroller. Please send your bids for implementation of the project!

Video stitching or image stitching in FPGA. Using 2 webcam taking images from webcams, creating a larger (panaromic) image . Matlab HDL Coder or VHDL can be used. All the parts including codes and all FPGA process must be done

Face recognition is very important technology in view of security threats world is facing. It is implemented on defense campuses, security building and offices. Now days it is used in social networking sites like Facebook and workout. GAFF is used for field programmable gate array.

Hi Botond We are interested in FPGA development. Our requirement is to take in a video stream in either DVI or HDMI. To decode the video data into RGB values and scale the value of each with an 8 bit value. This brightness value will be supplied on a 3 line interface consisting of clock, data and update. The data is 24 bits shifted in on the rising edge of the clock line, after all 24 bits are clocked in the update will pulse low. After doing the scaling the RGB video data is then recombined with the control bits (delayed if needed to account for scaling time) and then reassembled into either HDMI or DVI. A control pin will configure operation mode, low for HDMI and high for DVI. Xilinx FPGA preferred ideally with internal configuration memory ....the XC3S50AN would...

Reduced computational complexity PTS algorithm, which aims to reduce computational complexity and achieve the same performance for PAPR reduction compared to conventional PTS approaches, is proposed. In the algorithm, a low complexity phase weighting process is implemented, and the key point is the inherent relationship between phase weighting sequences is considered, which results in simplifying the computation for candidate signals The requirement from the project is to create a block simulink depicting the PAPR reduction technique - Transmitter [refer fig 3 of attached paper] and corrosponding receiver for the same. Explanation of each line on Matlab code Refer attached document for further details Project deliverables: 1. Matlab codes and Simulink block 2. Description of ...

Abstract—This paper demonstrates an FPGA implementation of the Reed-Solomon, RS(255,239), codec architecture for the OTN G.709. The RS codec is designed to occupy the least amount of logic blocks, be fast and parameterizable. I am presenting an efficient implementation of the encoder algorithm on reconfigurable devices in addition to a non-finalized version of the decoder. Both encoder and decoder are synthesized to Altera’s StratixII and benchmarks are run against Altera’s Reed Solomon Code. Xelic’s encoder is measured to be about half the size of Altera’s encoder. Effort on optimizing Xelic’s decoder is underway to have an efficient implementation of the decoder algorithm.

I am looking for developers skilled with video transmission as well as using FPGA microcontrollers. This Proof of Concept is to demonstrate control of an AXIS IP camera along with video routing techniques. This project is broken down into tasks: 1. Stream video data from an AXIS IP Camera using its HTTP based API 2. Store video onto a Secure Digital (SD) card on a development board that uses the Xilinx processor 3. Send a video stream to a Remote Video Viewer which is small program written by you (the contractor). 4. Display live video through the HDMI output port that is on the development board The above steps are detailed further in the attached document. At the end of this project the contractor will deliver: 1. Working source code for the ATLYS development board...

The goal of this project is to implement the Rijndael (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. The algorithm lends itself well towards parallel computations acting on separate sections of the data during the different stages in each round. AES encryption is done in rounds, similar to DES and IDEA. Each round of encryption consists of four steps. These steps are byte substitution, row shifting, column transformation, and round key addition. The interaction of these steps can be seen in more detail in the figures below.