Zedboardmunkák

I having a Application project on vitis that i need to run to see the result on zynq zedboard . Since i dont have the board , im looking for someone to run it and instruct me how to set up the zedboard to run the project. Im working on Windows OS

Please bid only if you have past experience working on Zynq PS system. You must also have your own Zynq 7000 based development board. This project requires implementation of PS side SPI0, SPI1 and DMA to move data from 2 SPI slaves to onboard DDR3 memory. 1) Use your own Zynq 7000 based development board (e.g Microzed, Zedboard etc having DDR3 memory) that you already have. 2) To this board connect 2nos. of SPI EEPROM. We will supply you with the EEPROM boards with jumper cables on other end to connect to your development board. 3) 1st EEPROM connects to PS SPI0 & 2nd EEPROM connects to PS SPI1 interface. 4) Both the SPI interfaces will be configured to operate at 25MHz SPI clock frequency. 5) Configure the PS DMA (2 channels would be needed) for both PS SPI0 & PS SPI1 ...

I am seeking a technical writer and system improvement expert to help me with my project. Specifically, I need help with improving the software aspect of the system which includes C, Vivado, Python, and Ethernet. The ideal candidate should have experience with VHDL and ZedBoard at an intermediate level. The following skills and experience are required for this project: - Technical writing for system documentation - Knowledge of software (C, Vivado, Python, Ethernet) - Intermediate experience with ZedBoard and VHDL If you possess the above skills and experience, please apply for this project.

I am looking for a freelancer who can assist me with technical writing for my project that involves the use of Zedboard SoC, ADC, filter, ethernet, and Python code. The desired end goal of the project is to write a technical report with a detailed explanation of the project. I will need assistance with coding in Python to communicate with the SoC and computer. The technical report should include a detailed explanation of the project, including the use of Zedboard SoC, ADC, filter, ethernet, and Python code.

1- Signal processing using ML on a computer (C Language) 2- using Single and dual ARM (C Language) 3-using FPGA Zedboard programmable logic (VHDL Language)

with the following requirements: 1. On/Off button. 2. Enter the frequency. 3. Enter the duty cycle for all the 16PWM signals. 4. Read the value on the previous address variable. 5. Selection of Communication port (COM port). Establish the connection between GUI and Zynq Zedboard 7000 through UART

We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transferring data of around 75k samples of 16 bit each to PC. Its taking around 3 min for transfer. Need work on data transfer rate and improve the same.

The project is to develop an application based on FPGA development board with interfacing Analog Eval. board for processing audio signal. Here is details : H/W will be used : 1- Zynq Zedboard or MPSOC development board. 2- AD7134 dual chip AD Development board. Both boards connected by FMC LPC/HPC connector. S/W - F/W : 1- AD7134 is supported by AD and it has all firmware required to interface to many fpga board, so we can use this ready HDL/DRIVER for interfacing the AD7134 to our fpga board. 2- interfacing to PC through Ethernet with ready library "LIBIIO" or using "Matlab FPGA data capture". We have all hardware development boards on hand, can use it remotely. Any details will be discussed in details.

...given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-2.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-2.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-2.4 Provide a clean code with the associated documentation. P...

...given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-2.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-2.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-2.4 Provide a clean code with the associated documentation. P...

...sample from audio Codec, TOD data from GPS receiver and perform base band digital modulations on this data/audio samples and should convert into a fixed analog IF frequency. • The architecture should be like SDR architecture, base band I/Q samples will be modulated in to base band modulated I/Q samples. To implement this architecture the following design has been adopted by us. We have selected "Zedboard” ZYNQ/FPGA for base band signal processing & AD9361 RF Agile transceiver as a RF front end. For Data Packetization, Data enocding, decoding we are using ZYNQ/ARM processor. From the available open sources we have designed HDL project in FPGA (VIVADO-2020.2) and Software project in Xilinx Vitis and Modulator IP cores generated from Simulink model based deisign...

FPGA Application Project, guidance on PL to PS communication logic.

I'm looking for a SoC / Firmware engineer who has rich experience in Vivado 2019.1 / PetaLinux programming. The board is a Zedboard (Z7020) connecting to the Ominivision Camera (OG02B10) via a customised board. The project consists of -) Solving our current Vivado issue with a Digilent PCAM camera -) Developping a customised IP block for the Omnivision OG02B10 camera sensor -) Creating a Vivado design (2019.1) to collect image frames from the omnivision cameras and to save them into the SD cards (in jpeg format) -) Provide documentation on the code

I'm looking for a FPGA / Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The board is a Zedboard (Z7020) connecting to the RF front-end (MAX2771 EK). The project consists of -) Creating in baremetal application a Vivado pipeline (2019.1) to collect RF data from the MAX2771 to be transferred to the FPGA side of the Zynq SoC -) Optimise our code for GPS position real-time application (FFT / IFFT / Signal Correlation) -) Provide documentation on the code

Hi, I need you to adapt this project () to Zedboard. Github's link is on the video description.

I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

1- I want to create a pulse generator 2- receive the analog signal using XADC Header in FPGA_SOC Zedboard. 3-display the signal received by XADC on PC using Ethernet with MatLab or LabVIEW or python interface this work in VHDL and C language.

1- I want to measure the analog signal using zedboard. I want to receive the analog signal by using the XADC header in zedboard SOC buy using the ip core in vivado and the output by using the Ethernet to pc finaly read the data from the ethernet by using matlab, Labview or python soft osaloscop. 2- create pulse generator sequence pulse.(vhdl ip core) 3- signal processing

Hello , I need someone who can design a IP Catalog using Vivado HLS and with OpenCV libraries and this need to work on ZedBoard. This might be an easy task but I'm new in this platform. I was trying to build a simple Optical Mark Reader. But in this project I just need to package the IP with these codes no need to finish C code. If you check the sources you'll get it. I need this finished within 2 days.

1. You should have an AMBA AXI based design with an ARM processor. 2. Let us say, from your computer you transfer an image to a memory for Harris Corner detection. 3. Once you release the reset, your design should read the image in the memory and calculate the corners and generate an output image, 4. There should be an indication saying the HC is done; then you should read the image from memory using an ARM processor and display on your computer. 5. For a final demo, a sequence images should be used which will be processed one after the other in sequence.

400MSPs data acquisition using Zedboard and FMC ADC

we want to acquire analog data at 400MSPs and average 2^n times where nis 1,2,3... max16. each trace for 100us and finally, do the right shift n times to get the average. then transmit data to pc using ethernet or usb or serial.

I want to implement a face recognition algorithm on Xilinx pynq z2 or a zedboard card.

Hi, I have put together a project for Zynq Zedboard and am not very experienced with FPGA/Vivado. My problem currently is I have many warning on synthesis and removal of some registers so I need some help with issues I am having. The custom IP is a frequency counter with an AXI4 Full bus to the PS as well as an AXI Lite from the PS for configuration. I'm hoping to get to the stage of reading and writing from the PS for now

A simple project where you need to work with zynq GPIOs. Design a fsm and connect its values on the gpio of the boardProject is achivable in 2 days, but proper documentation needed to done.

I need to implement a true random generator on zedboard fpga. noise source will be ECG signal.

I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.

I am fatima zohra , working as intern for a startup company. I need object tracking to be implemented on xilinx zedboard for a HD video. The application should be able to track an object/person of interest from the camera captured video using lucas- kanade optical flow estimation. The output should be obtained through HDMI out which can be connected to computer/ TV screen. Tools like MATLAB , xilinx system generator, xilinx model generator, xilinx Vivado can be used for simplicity in programming

Implement a UDP communication protocol in VHDL to transmit and receive UDP packets. A linux based PC will send a UDP packet of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard. Important note, your implementation should ONLY use PL part of the fpga and no FPGA specific units (like cpu cores, AXI bus, HARD mac chip interface unit,...) should be used. VHDL code should be transferable between different fpga brands, and use minimum possible amount of resources. You will be provided a c++ code which does the mentioned test on PC side.

I need a detailed video tutorial which includes the following material: - A thorough tutorial with several examples on zedboard XADC. - A thorough tutorial with several examples showing: 1. reading an input analogue signal through XADC 2. processing it in "Xilinx System Generator" and 3. showing the results on the oscilloscope. The video tutorial should be at least 1 hour. All files and scripts should be shared. The project should be done in VHDL code. The whole procedure must be done in details and questions must be answered clearly.

The project requires hardware & software design, implementation and testing of a simple & basic multi-function digital clock using Zynq 7000 ZED board. See attached for further information and specifications.

I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

-video display on to the monitor -filtering on the video on vivado software (VHDL)

I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features.

i need to port existing TARP OpenHPSDR-Firmware to new hardware have many change to make 1-) migrate from Altera to Xilinx ZedBoard Zynq-7000 2-) ADC chip swap AD9467 ( 2 x original clock speed) 3-) low speed Audio part ADC/DAC no need to be ported at this time 4-) use MAC and PHY of the ZedBoard 5-) all code need to releasable into open source link to original source code (ANAN-10%20and%20100) both ADC DAC will be provided as a FMC card once work on the ZedBoard project will move to a new board whit PCIe interface this is to be considered but it on a different project be a ham radio operator is a great advantage on that project

*The purpose and overview of my project I am designing easy application on zynq programmable soc. But it doesn't work correctly. *The application I am designing I am designing the exact same design as the link. C code which run on PS core [6] = 11 RxBuffer[7] = 12 RxBuffer[8] = 13 RxBuffer[9] = 14. … The first 5 values of the beginning is wrong. *Notice I want to use C code for high-synthesizing and application code. Don't use C++ code. *Deliverable *design file and project file which run correctly *the explanation why my design doesn't work *My environment Vivado 2015.4 Vivado HLS 2015.4 SDSoC 2015.4 Board zedboard, zybo

*The purpose and overview of my project I am designing easy application on zynq programmable soc. But it doesn't work correctly. *The application I am designing I am designing the exact same design as the link. C code which run on ...RxBuffer[6] = 11 RxBuffer[7] = 12 RxBuffer[8] = 13 RxBuffer[9] = 14. … The first 5 values of the beginning is wrong. *Notice I want to use C code for high-synthesizing and application code. Don't use C++ code. *Deliverable *design file and project file which run correctly *the explanation why my design doesn't work *My environment Vivado 2015.4 Vivado HLS 2015.4 SDSoC 2015.4 Board zedboard, zybo *I am thinking the budget is 8000JPY.

...project I want a simple module that is able to do the following on a Xilinx ZedBoard: 1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY 2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data INPUTS: 1. 256 BITKEY 2. selector BIT for encrypt decrypt (the output needs an XOR for decrypt) 3. stream of data as 256 bit 'chunks'. The architecture here should be trivial to support a driver easily. OUPUTS: 1. 256 AESKEY 2. stream of encrypted/decrypted data as 256 'chunks' DOCUMENTATION: This should be the bulk of the work; There needs to be diagrams and specifications for reproduction on another ZedBoard. This should include: 1...

i want to hire someone who can do Image processing with Vhdl and c programming. i need to make a vivado program, where i can input music note sheet (jpeg format for example) and generate output (text file). the output needs to be music note values. so later we can input same text file on vivado and using Zedboard to play the music

build an SDK(software development kit)(procedure i have in a manual)

I/Q Interface to analog device AD9361 for the ADS-B RF Interface (1090 MHz with 8Msps) the existing algorithms on the Zync FPGA. The Algorithms are the decoding of the ADS-B signal which is PWM based. the Algorithm to SW (Dual ARM) and HW (FPGA)

Capture a Depth image in Kinect v1 and apply smoothing filter using FPGA (Zedboard). Example filter:

We want to implement some functions on FPGA boards like Xula, Zedboard, etc. - Freelancer should be able to assist our team in achieving its goals by developing and testing the modules/functions.

Hello, I need a program in FPGA (in Xilinx) able to display RGB and Microsoft Kinect Depth cameras on the VGA output of the Zedboard.

I need to program a ZEDboard to output SPI to control a PLL board. The project requires PlanAhead knowledge and Cprogramming. Basically, I need someone with the knowledge of how to route and program the output. In the attached is the chip we need the SPI to control it. Only pins required is the sck, SDI, SEN, LD_SDO. Thanks!

I need someone to design a simple 3x3 verilog convolution module in Xilinx to work on the Zedboard. The project must be able to take in an image from a webcam and display it on a monitor. The user must be able to convolte the image by means of the push buttons on the Zedboard.

I need to develop a program capable of running a Kinect sensor on the Zedboard. The program should be able to trace circles in the image and display the video output (RGB and Depth camera) on the VGA interface of the Zedboard.

I need to develop a program capable of running a Kinect sensor on the Zedboard. The program should be able to trace circles in the image and display the video output (RGB and Depth camera) on the VGA interface of the Zedboard.

I need to develop a program capable of running a Kinect sensor on the Zedboard. The program should be able to trace circles in the image and display the video output (RGB and Depth camera) on the VGA interface of the Zedboard.

I need to develop a program capable of running a Kinect sensor on the Zedboard. The program should be able to trace circles in the image and display the video output (RGB and Depth camera) on the VGA interface of the Zedboard.